# Learn VHDL Code for Non Restoring Division Algorithm and Serial Adder in Easy Steps

## Non Restoring Division Algorithm: A VHDL Code Guide for Serial Adder Circuit

In this article, you will learn how to implement a non restoring division algorithm in VHDL for serial adder design. You will also understand the basic concept and working of the algorithm, as well as its advantages and disadvantages.

## Non Restoring Division Algorithm Vhdl Code For Serial Adder

## What is Non Restoring Division Algorithm?

Non restoring division algorithm is a method of performing binary division in hardware. It is based on the principle of successive approximation, where the quotient is obtained bit by bit by comparing the partial remainder with the divisor. The algorithm does not restore the partial remainder to its original value if it becomes negative after a subtraction, unlike the restoring division algorithm. Instead, it adds the divisor back to the partial remainder if it is negative at the end of each iteration. This reduces the number of operations and simplifies the hardware implementation.

## How Does Non Restoring Division Algorithm Work?

The non restoring division algorithm can be explained by the following steps:

Initialize the quotient Q and the partial remainder A to zero.

Shift the dividend D left by one bit and place it in A.

Subtract the divisor S from A and place the result in A.

If A is positive or zero, set the least significant bit of Q to 1. Otherwise, set it to 0.

Repeat steps 2 to 4 until all bits of D are processed.

If A is negative, add S to A and place the result in A.

The final value of Q is the quotient and the final value of A is the remainder.

## How to Implement Non Restoring Division Algorithm in VHDL for Serial Adder Design?

To implement non restoring division algorithm in VHDL for serial adder design, you need to use a finite state machine (FSM) with four states: idle, shift, subtract, and add. The FSM controls the inputs and outputs of a serial adder/subtractor module that performs the arithmetic operations on A and S. The FSM also generates a clock signal for shifting D and Q. The following diagram shows the block diagram of the serial divider:

![Serial Divider Block Diagram](__https://i.imgur.com/9tXlZ7x.png__)

The following code shows an example of VHDL implementation of non restoring division algorithm for serial adder design:

```vhdl

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity SerialDivider is

port(

clk : in std_logic; -- system clock

rst : in std_logic; -- reset signal

start : in std_logic; -- start signal

D : in unsigned(15 downto 0); -- dividend input

S : in unsigned(15 downto 0); -- divisor input

Q : out unsigned(15 downto 0); -- quotient output

R : out unsigned(15 downto 0); -- remainder output

done : out std_logic -- done signal

);

end SerialDivider;

architecture Behavioral of SerialDivider is

-- state enumeration

type state_type is (idle, shift, subtract, add);

signal state : state_type;

-- serial adder/subtractor module

component SerialAdderSubtractor is

port(

clk : in std_logic;

rst : in std_logic;

en : in std_logic;

mode : in std_logic; -- 0 for add, 1 for subtract

A : inout unsigned(15 downto 0);

B : in unsigned(15 downto 0)

);

end component;

-- internal signals

signal A_reg : unsigned(15 downto 0); -- partial remainder register

signal Q_reg : unsigned(15 downto 0); -- quotient register

signal D_reg : unsigned(15 downto 0); -- dividend register

signal S_reg : unsigned(15 downto 0); -- divisor register

signal count : integer range 0 to 16; -- counter for iterations

signal en_addsub : std_logic; -- enable signal for adder/subtractor

signal mode_addsub : std_logic; -- mode signal for adder/subtractor

begin

-- instantiate serial adder/subtractor module

U1: SerialAdderSubtractor port map(

clk => clk,

rst => rst,

en => en_addsub,

mode => mode_addsub,

A => A_reg,

B => S_reg

);

-- state transition process

process(clk, rst)

begin

if rst = '1' then -- asynchronous reset

state <= idle;

count <= 0;

en_addsub <= '0';

mode_addsub <= '0';

done <= '0';

elsif rising_edge(clk) then -- synchronous logic

case state is

when idle => -- wait for start signal

if start = '1' then

state <= shift; -- go to shift state

count <= count + 1; -- increment counter

en_addsub <= '1'; -- enable adder/subtractor

mode_addsub <= '1'; -- set mode to subtract

done <= '0'; -- clear done signal

else

state <= idle; -- stay in idle state

count <= 0; -- reset counter

en_addsub <= '0'; -- disable adder/subtractor

mode_addsub <= '0'; -- set mode to add

done <= '0'; -- clear done signal

end if;

when shift => -- shift dividend and quotient registers

if count < 16 then

state <= subtract; -- go to subtract state

count <= count + 1; -- increment counter

en_addsub <= '1'; -- enable adder/subtractor

mode_addsub <= '1'; -- set mode to subtract

done <= '0'; -- clear done signal

else

state <= add; -- go to add state

count <= count + 1; -- increment counter

en_addsub <= '1'; -- enable adder/subtractor

mode_addsub <= '0'; -- set mode to add

done <= '0'; -- clear done signal

end if;

when subtract => -- subtract divisor from partial remainder

if A_reg(15) = '0' then

state <= shift; -- go to shift state

count <= count + 1; -- increment counter

en_addsub <= '1'; -- enable adder/subtractor

mode_addsub <= '1'; -- set mode to subtract

done <= '0'; -- clear done signal

else

state <= shift; -- go to shift state

count <= count + 1; -- increment counter

en_addsub <= '1'; -- enable adder/subtractor

mode_addsub <= '0'; -- set mode to add

done <= '0'; -- clear done signal

end if;

when add => -- add divisor to partial remainder if negative

if A_reg(15) = '1' then

state

## What are the Advantages and Disadvantages of Non Restoring Division Algorithm?

Non restoring division algorithm has some advantages and disadvantages compared to other methods of binary division, such as restoring division, SRT division, or Newton-Raphson division. Here are some of them:

### Advantages

Non restoring division algorithm is simpler than restoring division algorithm because it does not require restoring the partial remainder to its original value if it becomes negative after a subtraction.

Non restoring division algorithm reduces the number of operations and simplifies the hardware implementation because it only requires addition and subtraction, and no multiplication or division.

Non restoring division algorithm can be easily implemented using a finite state machine (FSM) with four states and a serial adder/subtractor module.

### Disadvantages

Non restoring division algorithm is slower than other methods that use higher radices or parallelism, such as SRT division or Newton-Raphson division, because it only produces one bit of quotient per iteration.

Non restoring division algorithm may require an extra addition at the end if the partial remainder is negative, which increases the latency and complexity.

Non restoring division algorithm may not work for signed integers or fractional numbers, unless some modifications are made to handle the sign and decimal point.

## How to Design a Finite State Machine for Non Restoring Division Algorithm?

A finite state machine (FSM) is a model of computation that consists of a set of states, a set of inputs, a set of outputs, and a transition function that maps each state and input to a new state and output. A FSM can be used to control the logic and timing of a serial divider based on non restoring division algorithm. The following diagram shows an example of a FSM for non restoring division algorithm:

![FSM for Non Restoring Division Algorithm](__https://i.imgur.com/6wZyf9L.png__)

The FSM has four states: idle, shift, subtract, and add. The inputs are clk (system clock), rst (reset signal), start (start signal), D (dividend input), S (divisor input), and A (partial remainder register). The outputs are Q (quotient output), R (remainder output), done (done signal), en_addsub (enable signal for adder/subtractor), and mode_addsub (mode signal for adder/subtractor). The transition function is as follows:

When rst = '1', the FSM goes to idle state and resets all the outputs and internal signals.

When start = '1' in idle state, the FSM goes to shift state and initializes the counter, enables the adder/subtractor, sets the mode to subtract, and clears the done signal.

When count < 16 in shift state, the FSM goes to subtract state and increments the counter, enables the adder/subtractor, sets the mode to subtract, and clears the done signal.

When count = 16 in shift state, the FSM goes to add state and increments the counter, enables the adder/subtractor, sets the mode to add, and clears the done signal.

When A(15) = '0' in subtract state, the FSM goes to shift state and increments the counter, enables the adder/subtractor, sets the mode to subtract, and clears the done signal.

When A(15) = '1' in subtract state, the FSM goes to shift state and increments the counter, enables the adder/subtractor, sets the mode to add, and clears the done signal.

When A(15) = '1' in add state, the FSM goes to idle state and disables the adder/subtractor, sets the mode to add, and sets the done signal.

When A(15) = '0' in add state, the FSM stays in add state and disables the adder/subtractor, sets the mode to add, and sets the done signal.

## Conclusion

In this article, we have learned how to implement a non restoring division algorithm in VHDL for serial adder design. We have also understood the basic concept and working of the algorithm, as well as its advantages and disadvantages. We have also seen how to design a finite state machine for non restoring division algorithm and how to use a serial adder/subtractor module for the arithmetic operations. Non restoring division algorithm is a simple and efficient method of performing binary division in hardware, but it may not be suitable for all applications and data types. We hope this article has been helpful and informative for you. b99f773239

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